This invention relates to a speed detection apparatus. More particularly, it relates to a speed detection apparatus in a control system for an electric equipment subject to a variable speed control, according to which the instability of the control system attributed to mechanical play, etc. within the control system can be absorbed without effecting the responsiveness thereof by rendering a sampling interval variable.
A speed detection apparatus is often used in combination with a speed control system, and it is employed as, for example, the variable speed system of an electric motor such as a thyristor Ward-Leonard system in a steel plant. FIG. 1 is a block diagram of the control system. Numeral 1 designates a D.C. motor, numeral 2 the speed detection apparatus of the specified type which detects the rotating speed of the motor, and numeral 3 a speed controller which provides a reference current command according to the difference between the detected speed and a set speed. On the other hand, numeral 4 indicates a three-phase A.C. power source, and numeral 5 a converter which converts a three-phase alternating current into a variable D.C. voltage source. Shown at numeral 6 is a current sensor which senses the value of current to be fed to the converter. A current controller 7 generates data for adjusting the output voltage of the converter 5, according to the difference between the actual current provided from the current sensor 6 and the reference current command from the speed controller 3. Numeral 8 denotes a gate control circuit which enables or disables switching elements such as thyristors constituting the converter 5, according to the data from the current controller 7. The speed control of the D.C. motor 1 can be performed by varying a feed voltage to the motor. The converter 5 is of the type which can change-over a plus voltage output mode and a minus voltage output mode in accordance with the reference current delivered from the speed controller 3.
In such a system, the control response is enhanced as the sampling interval for speed detection is made shorter. In the presence of play, etc. which occurs in a mechanical system due to, for examples, gears, however, when the sampling interval is short, a great pulsation appears in the detected speed due to the influence of the play, and also the reference current command from the speed controller 3 pulsates greatly. Under such a condition, in a case where a torque to be generated may be small due to light load, a small current average value will incur a state in which the reference current command pulsates between a plus value and a minus value due to the speed pulsation. In consequence, the changeover of the converter for generating a plus voltage and a minus voltage occurs frequently, and the control system becomes unstable under the influence of the dead time of the change-over, etc. When the sampling interval is lengthened in such event, a momentary great pulsation is absorbed, and hence, the fluctuation of the detected speed decreases to stabilize the control system. From the viewpoint of practical use, however, there are many cases where a great torque is required due to a heavy load on the motor as in the case of, e.g., rolling. In such cases, the average current becomes large, and the current pulsation becomes small enough to be neglected relative to the average current. Under this condition, therefore, the sampling interval needs to be set short so as to enhance the responsiveness. In order to stabilize the control system in the whole operating range thereof, accordingly, the sampling interval needs to be varied according to the load.
A prior-art speed detection apparatus of the specified type applied to a variable speed system is disclosed in Japanese Utility Model Registration No. 53-53776. FIG. 2 is a block diagram of the apparatus. A pulse generator 21 generates pulses (denoted by .phi.) having a frequency proportional to a speed, and a first counter 22 counts the pulses. On the other hand, a pulse oscillator 23 generates pulses (denoted by CLK) having a fixed frequency quite independently of the generator 21, and a second counter 24 counts the pulses. In accordance with a signal provided from a reset circuit 25 at a fixed period T.sub.s, the count values of the first counter 22 and the second counter 24 are simultaneously stored into a first register 26 and a second register 27, respectively, while at the same time the first counter 22 and the second counter 24 have their count values cleared to zero to count the numbers of the pulses from zero again. Letting N.sub..phi. and N.sub.s denote the count values stored in the first register 26 and the second register 27 at this point of time, respectively, and 1/t denote the frequency of the pulses oscillated from the oscillator 23, the sampling period becomes: EQU T.sub.s =N.sub.s t (1)
Since the number of revolutions N is a value proportional to the number of pulses generated from the pulse generator 21 within a unit time, it can be expressed as: ##EQU1## The rotating speed N can accordingly be obtained in such a way that a CPU 28 executes the operation of Equation (2) by receiving the respective values N.sub..phi. and N.sub.s of the first register 26 and the second register 27. Here, K.sub.a and K.sub.b are proportion constants. That is, the period T.sub.s is the speed measuring period and also serves as the sampling period for the speed detection. This period T.sub.s is determined as follows. FIG. 3 illustrates timings for determining T.sub.s. The pulses CLK are generated at the predetermined intervals t by the oscillator 23, and they are counted by the second counter 24. A value N.sub.c is previously set in the counter 24 in hardware fashion, and the point of time at which the next pulse .phi. after the count value has reached the value N.sub.c is set as the end of the period T.sub.s. Accordingly, when the period of time in which the count value of the second counter 24 reaches N.sub.c is denoted by T.sub.c, EQU T.sub.c =N.sub.c t (4)
holds, and T.sub.s .gtoreq.T.sub.c holds. T.sub.s =.infin. holds for an extremely low speed, but in the ordinary state in which at least one pulse .phi. is generated during the period T.sub.c, the rise of the pulse .phi. follows the period T.sub.c before a further period T.sub.c lapses at the latest. For this reason, EQU 2T.sub.c .gtoreq.T.sub.s .gtoreq.T.sub.c ( 5)
holds ordinarily, and T.sub.s is limited by T.sub.c.
In the prior-art speed detection apparatus, the frequency 1/t of the oscillator 23 and the set value N.sub.c of the counter 24 are determined by hardware, and they are not easily altered but are fixed during the operation of the speed detection apparatus, so that the sampling period T.sub.s is substantially fixed as (2 T.sub.c .gtoreq.T.sub.s .gtoreq.T.sub.c). Therefore, in case of applying the apparatus to the speed control system of the motor as shown in FIG. 1, when the sampling interval T.sub.s is fixed to a short magnitude, a favorable responsiveness is attained, but the control system might become unstable at the time of a light load. Conversely, when the sampling interval T.sub.s is set at a long magnitude, the control system is stabilized also at the time of a light load, but the responsiveness degrades disadvantageously.